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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2005, zarlink semiconductor inc. all rights reserved. features ? compliant with etsi 300 744 dvb-t, unified nordig and dtg performance specifications ? high performance with fast fully blind acquisition and tracking capability ? low power consumption: less than 0.32 w, and eco-friendly standby and sleep modes ? digital filtering of adjacent channels ? single 8 mhz saw filter for 6, 7 & 8 mhz ofdm ? superior single frequency network performance ? fast agc to track out signal fades ? good doppler tracking capability ? enhanced frequency capture range to include triple offsets ? external 4 mhz clock or single low-cost 20.48 mhz crystal, tolerance up to +/-200 ppm ? automatic mode (2k/8k), guard and spectral inversion detection ? very low driver software overhead due to on-chip state-machine control ? novel rf level detect facility via a separate adc ? pre and post viterbi-decoder bit error rates, and uncorrectable block count applications ? digital terrestrial set-top boxes ? integrated digital televisions ? personal video recorders ? pc-tv receivers ? portable applications description the ZL10353 is a superior fourth generation fully compliant etsi ets300 744 cofdm demodulator that exceeds, with margin, the performance requirements of all known dvb-t digital terrestrial television standards, including unified nordig and dtg. june 2005 ordering information ZL10353qcg 64 pin lqfp trays, bake & drypack ZL10353qcg1 64 pin lqfp* trays, bake & drypack ZL10353qcf 64 pin lqfp tape & reel, bake & drypack ZL10353qcf1 64 pin lqfp* tape & reel,bake & drypack *pb free matte tin -10 c to +80 c ZL10353 fully compliant nordig unified cofdm digital terrestrial tv (dtv) demodulator data sheet figure 1 - block diagram
ZL10353 data sheet 2 zarlink semiconductor inc. a high performance 10 bit on-chip adc is used to sample the 44 or 36 mhz if analogue signal. advanced digital filtering of the upper and lower channel enables a single 8 mhz channel saw filter to be used for 6, 7 and 8 mhz ofdm signal reception. all sampling and other internal clocks are derived from a single 20.48 mhz crystal or a 4 mhz clock input, the tolerance of which may be relaxed as much as 200 ppm. the ZL10353 has a wide frequency capture range able to automatically compensate for the combined offset introduced by the tuner xtal and broadcaster triple frequency offsets. an on-chip state machine controls all acquisition and tracking operations of the ZL10353 as well as controlling the tuner via a 2-wire bus. any frequency range can be automatically scanned for digital tv channels. this mechanism ensures minimal interaction, maximum flexibility and fast acquisition - very low software overhead. also included in the design is a 7-bit adc to detect the rf signal strength and thereby efficiently control the tuner rf agc. users have access to all the relevant signal quality information, including input signal power level, signal-to-noise ratio, pre-viterbi ber, post-viterbi ber, and the uncorrectable block counts. the error rate monitoring periods are programmable over a wide range. the device is packaged in a 10 x 10 mm 64-pin lqfp and is very low power.
ZL10353 data sheet 3 zarlink semiconductor inc. 1.0 pin & package details 1.1 pin outline figure 2 below shows the basic, non-diversity, pin functions of the ZL10353. the device can effectively be set up in seven different pin configurations, so for brevity only this version is shown. figure 2 - pin outline
ZL10353 data sheet 4 zarlink semiconductor inc. 1.2 pin allocation pin function pin function pin function pin function 1 vss 17 sadd1 33 vdd 49 mdo0/dv0/ dv1 2 vdd 18 sadd0 34 rflev 50 mdo1/dv1/ dv3 3 vss 19 cvdd 35 clk2/gpp0 51 mdo2/dv2 4 clk1 20 vss 36 data2/gpp1 52 mdo3/dv3/ dv1 5 data1 21 pllvdd 37 cvdd 53 mdo4/dv4/ dv0 6irq /dv4/dv0 22 pllgnd 38 vss 54 vdd 7 cvdd 23 xti 39 cvdd 55 vss 8vss 24xto 40vss 56mdo5 9 reset 25 vss 41 agc2/gpp2/dvval 57 mdo6 10 sleep 26 plltest 42 agc1 58 mdo7 11 status/dv3 / dv1 27 oscmode 43 gpp3/dvclk 59 cvdd 12 sadd4/dv2 28 avdd 44 smtest 60 vss 13 vdd 29 agnd 45 vdd 61 moclk/dvclk 14vss 30vin 46vss 62bkerr 15 sadd3/dv1/ dv3 31vin 47mostrt 63miclk 16 sadd2/dv0/ dv1 32 agnd 48 moval/dvval 64 cvdd table 1 - pin names - numeric function pin function pin function pin function pin agc1 42 gpp3/dvclk 43 plltest 26 vdd 54 agc2/gpp2/dvval 41 irq /dv4/dv0 6 pllvdd 21 vin 30 agnd 29 mdo0/dv0/ dv1 49 reset 9 vin 31 agnd 32 mdo1/dv1/ dv3 50 rflev 34 vss 1 avdd 28 mdo2/dv2 51 sadd0 18 vss 3 bkerr 62 mdo3/dv3/ dv1 52 sadd1 17 vss 8 clk1 4 mdo4/dv4/ dv0 53 sadd2/dv0/dv1 16 vss 14 clk2/gpp0 35 mdo5 56 sadd3/dv1/dv3 15 vss 20 table 2 - pin names - alphabetical order
ZL10353 data sheet 5 zarlink semiconductor inc. 1.3 pin description cvdd 7 mdo6 57 sadd4/dv2 12 vss 25 cvdd 19 mdo7 58 sleep 10 vss 38 cvdd 37 miclk 63 smtest 44 vss 40 cvdd 39 moclk/dvclk 61 status/dv3/ dv1 11 vss 46 cvdd 59 mostrt 47 vdd 2 vss 55 cvdd 64 moval/dvval 48 vdd 13 vss 60 data1 5 oscmode 27 vdd 33 xti 23 data2/gpp1 36 pllgnd 22 vdd 45 xto 24 pin no name pin description i/o type v ma mpeg pins 47 mostrt mpeg packet start o cmos tristate 3.3 1 48 moval (or dvval-o) mpeg/diversity data valid o 3.3 1 49-53, 56-58 mdo(0:4)/dv(0:4)-o mdo(5:7) mpeg/diversity data bus o 3.3 1 61 moclk (or dvclk-o) mpeg/diversity clock out o 3.3 1 62 bkerr block error o 3.3 1 63 miclk mpeg clock in i cmos 3.3 11 status (or dv3/1) status output or diversity data i/o 3.3 1 6irq (or dv4/0) interrupt output or diversity data i/o open drain 5 6 control pins 4 clk1 serial clock i cmos 5 5 data1 serial data i/o open drain 5 6 function pin function pin function pin function pin table 2 - pin names - alphabetical order (continued)
ZL10353 data sheet 6 zarlink semiconductor inc. 23 xti low phase noise oscillator i cmos 24 xto o 10 sleep device power down i 3.3 12, 15-18 sadd(4:0) serial address set i 3.3 12, 15, 16 sadd(4:0) dv2,1,0/2,3,4 serial address set or diversity data i/o i/o 3.3 3.3 17, 18 sadd(1:0) serial address set 3.3 44 smtest production test (only set low) i 3.3 35 clk2/gpp0 serial clock tuner i/o open drain 5 6 36 data2/gpp1 serial data tuner i/o 5 6 42 agc1 primary agc o 5 6 41 agc2/gpp2 secondary agc i/o 5 6 43 gpp(3) general purpose i/o i/o 5 6 9 reset device reset i cmos 5 27 oscmode crystal oscillator mode i cmos 3.3 26 plltest pll analogue test o (tristated) analog inputs 30 vin positive input i 31 vin negative input i 34 rflev rf level i supply pins 21 pllvdd pll supply s 1.8 22 pllgnd s 0 7, 19, 37, 39, 59, 64 cvdd core logic power s 1.8 2, 13, 45, 54, vdd i/o ring power s 3.3 1, 3, 8, 14, 20, 25, 38, 40, 46, 55, 60 vss core and i/o ground s 0 28 avdd adc analog supply s 1.8 29, 32 agnd s 0 33 vdd 2nd adc supply s 3.3 pin no name pin description i/o type v ma
ZL10353 data sheet 7 zarlink semiconductor inc. 2.0 functional description a functional block diagram of the ZL10353 ofdm demodulator is shown in figure 3. this accepts an if analogue signal and delivers a stream of demodulated soft decision data to the on-chip viterbi decoder. clock, timing and frequency synchronization operations are all digital and there are no analogue control loops except the agc. the frequency capture range is large enough for all practical applications. this demodulator has novel algorithms to combat impulse noise as well as co-channel and adjacent channel interference. if the modulation is hierarchical, the ofdm outputs both high and low priority data streams. only one of these streams is fec-decoded, but the fec can be switched from one stream to another with minimal interruption to the transport stream. figure 3 - ofdm demodulator diagram the fec module shown in figure 4 consists of a concatenated convolutional (viterbi) and reed-solomon decoder separated by a depth-12 convolutional de-interleaver. the viterbi decoder operates on 5-bit soft decisions to provide the best performance over a wide range of channel conditions. the trace-back depth of 128 ensures minimum loss of performance due to inevitable survivor truncation, especially at high code rates. both the viterbi and reed-solomon decoders are equipped with bit-error monitors. the former provides the bit error rate (ber) at the ofdm output. the latter is the more useful measure as it gives the viterbi output ber. the error collecting intervals of these are programmable over a very wide range.
ZL10353 data sheet 8 zarlink semiconductor inc. figure 4 - fec block diagram the fsm controller shown in figure 3 controls both the demodulator and the fec. it also drives the 2-wire bus to the tuner. the controller facilitates the automated search of all parameters or any sub-set of parameters of the received signal. it can also be used to scan any defined frequency range searching for ofdm channels. this mechanism provides the fast channel scan and acquisition performance, whilst requiring minimal software overhead in the host driver. the algorithms and architectures used in the ZL10353 have been optimized to minimize power consumption. 2.1 analogue-to-digital converter the ZL10353 has a high performance 10-bit analogue-to-digital converter (adc) which can sample a 6, 7 or 8 mhz bandwidth ofdm signal, with its spectrum centred at: ? 36.17 mhz if ? 43.75 mhz if ? 5 - 10 mhz near-zero if an on-chip programmable phase locked loop (pll) is used to generate the adc sampling clock. the pll is highly programmable allowing a wide choice of sampling frequencies to suit any if frequency, and all signal bandwidths. 2.2 automatic gain control an agc module compares the absolute value of the digitized signal with a programmable reference. the error signal is filtered and is used to control the gain of the amplifier. a sigma-delta modulated output is provided, which has to be rc low-pass filtered to obtain the voltage to control the amplifier. the programmable agc reference has been optimized. a large value for the reference leads to excessive adc clipping and a small value results in excessive quantization noise. hence the optimum value has been determined assuming the input signal amplitude to be gaussian distributed. the latter is justified by applying the central limit theorem in statistics to the ofdm signal, which consists of a large number of randomly modulated carriers. this reference or target value may have to be lowered slightly for some applications. slope control bits have been provided for the agcs and these have to be set correctly depending on the gain-versus-voltage slope of the gain control amplifiers.
ZL10353 data sheet 9 zarlink semiconductor inc. the bandwidth of the agc is set to a large value for quick acquisition then reduced to a small value for tracking. the agc is free running during ofdm channel changes and locks to the new channel while the tuner lock is being established. this is one of the features of ZL10353 used to minimize acquisition time. a robust agc lock mechanism is provided and the other parts of the ZL10353 begin to acquire only after the agc has locked. 2.3 if to baseband conversion sampling a 36.17 mhz if signal at 45 mhz results in a spectrally inverted ofdm signal centred at approximately 8.9 mhz. the first step of the demodulation process is to convert this signal to a complex (in-phase and quadrature) signal in baseband. a correction for spectral inversion is implemented during this conversion process. note also that the ZL10353 has control mechanisms to search automatically for an unknown spectral inversion status. 2.4 adjacent channel filtering adjacent channels, in particular the nicam digital sound signal associated with analogue channels, are filtered prior to the fft. 2.5 interpolation and clock synchronization ZL10353 uses digital timing recovery and this eliminates the need for an external vcxo. the adc samples the signal at a fixed rate, for example, 45.056 mhz. conversion of the 45.056 mhz signal to the ofdm sample rate is achieved using the time-varying interpolator. the ofdm sample rate is 64/7 mhz for 8 mhz and this is scaled by factors 6/8 and 7/8 for 6 and 7 mhz channel bandwidths. the nominal ratio of the adc to ofdm sample rate is programmed in a ZL10353 register (defaults are for 45 mhz sampling and 8 mhz ofdm). the clock recovery phase locked loop in the ZL10353 compensates for inaccuracies in this ratio due to uncertainties of the frequency of the sampling clock. 2.6 carrier frequency synchronization there can be frequency offsets in the signal at the input to ofdm, partly due to tuner step size and partly due to broadcast frequency shifts, typically 1/6 mhz. these are tracked out digitally, up to 1 mhz in 2 k and 8 k modes, without the need for an analogue frequency control (afc) loop. the default frequency capture range has been set to 286 khz in the 2 k and 8 k mode. however, these values can be increased, if necessary, by programming an on-chip register (see 6.4.1). it is recommended that a larger capture range be used for channel scan in order to find channels with broadcast frequency shifts, without having to adjust the tuner. after the ofdm module has locked (the afc will have been previously disabled), the frequency offset can be read from an on-chip register. 2.7 symbol timing synchronization this module computes the optimum sample position to trigger the fft in order to eliminate or minimize inter-symbol interference in the presence of multi-path distortion. furthermore, this trigger point is continuously updated to dynamically adapt to time-variations in the transmission channel. 2.8 fast fourier transform the fft module uses the trigger information from the timing synchronization module to set the start point for an fft. it then uses either a 2 k or 8 k fft to transform the data from the time domain to the frequency domain. an extremely hardware-efficient and highly accurate algorithm has been used for this purpose.
ZL10353 data sheet 10 zarlink semiconductor inc. 2.9 common phase error correction this module subtracts the common phase offset from all the carriers of the ofdm signal to minimize the effect of the tuner phase noise on system performance. 2.10 channel equalization this consists of two parts. the first part involves estimating the channel frequency response from pilot information. efficient algorithms have been used to track time-varying channels with a minimum of hardware. the second part involves applying a correction to the data carriers based on the estimated frequency response of the channel. this module also generates dynamic channel state information (csi) for every carrier in every symbol. 2.11 impulse filtering ZL10353 contains several mechanisms to reduce the impact of impulse noise on system performance. 2.12 transmission parameter signalling (tps) an ofdm frame consists of 68 symbols and a superframe is made up of four such frames. there is a set of tps carriers in every symbol and all these carry one bit of tps. these bits, when combined, include information about the transmission mode, guard ratio, constellation, hierarchy and code rate, as defined in ets 300 744. in addition, the first eight bits of the cell identifier are contained in even frames and the second eight bits of the cell identifier are in odd frames. the tps module extracts all the tps data, and presents these to the host processor in a structured manner. 2.13 de-mapper this module generates soft decisions for demodulated bits using the channel-equalized in-phase and quadrature components of the data carriers as well as per-carrier channel state information (csi). the de-mapping algorithm depends on the constellation (qpsk, 16qam or 64qam) and the hierarchy ( = 0, 1, 2 or 4). soft decisions for both low- and high-priority data streams are generated. 2.14 symbol and bit de-interleaving the ofdm transmitter interleaves the bits within each carrier and also the carriers within each symbol. the de-interleaver modules consist largely of memory to invert these interleaving functions and present the soft decisions to the fec in the original order.
ZL10353 data sheet 11 zarlink semiconductor inc. 2.15 viterbi decoder the viterbi decoder accepts the soft decision data from the ofdm demodulator and outputs a decoded bit-stream. the decoder does the de-puncturing of the input data for all code rates other than 1/2. it then evaluates the branch metrics and passes these to a 64-state path-metric updating unit, which in turn outputs a 64-bit word to the survivor memory. the viterbi decoded bits are obtained by tracing back the survivor paths in this memory. a trace-back depth of 128 is used to minimize any loss in performance, especially at high code rates. the decoder re-encodes the decoded bits and compares these with received data (delayed) to compute bit errors at its input, on the assumption that the viterbi output ber is significantly lower than its input ber. 2.16 mpeg frame aligner the viterbi decoded bit stream is aligned into 204-byte frames. a robust synchronization algorithm is used to ensure correct lock and to prevent loss of lock due to noise impulses. 2.17 de-interleaver errors at the viterbi output occur in bursts and the function of the de-interleaver is to spread these errors over a number of 204-byte frames to give the reed-solomon decoder a better chance of correcting these. the de-interleaver is a memory unit which implements the inverse of the convolutional interleaving function introduced by the transmitter. 2.18 reed-solomon decoder every 188-byte transport packet is encoded by the transmitter into a 204-byte frame, using a truncated version of a systematic (255,239) reed-solomon code. the corresponding (204,188) reed-solomon decoder is capable of correcting up to eight byte errors in a 204-byte frame. it may also detect frames with more than eight byte errors. in addition to efficiently performing this decoding function, the reed-solomon decoder in ZL10353 keeps a count of the number of bit errors corrected over a programmable period and the number of uncorrectable blocks. this information can be used to compute the post-viterbi ber. 2.19 de-scrambler the de-scrambler de-randomizes the reed-solomon decoded data by generating the exclusive-or of this with a pseudo-random bit sequence (prbs). this outputs 188-byte mpeg transport packets. the tei bit of the packet header may be set if required to indicate uncorrectable packets. 2.20 mpeg transport interface mpeg data can be output in parallel or serial mode. the output clock frequency is automatically chosen to present the mpeg data as uniformly spaced as possible to the transport processor. this frequency depends on the guard ratio, constellation, hierarchy and code rate. there is also an option for the data to be extracted from the ZL10353 with a clock provided by the user.
ZL10353 data sheet 12 zarlink semiconductor inc. 3.0 interfaces 3.1 2-wire bus 3.1.1 host the primary 2-wire bus serial interface uses pins: ? data1 (pin5) serial data, the most significant bit is sent first. ? clk1 (pin 4) serial clock. the 2-wire bus address is determined by applying vdd or vss to the sadd[4:0] pins. in tnim evaluation applications, the 2-wire bus address is 0001 111 r/w with the pins connected as follows: when the ZL10353 is powered up, the reset pin 9 should be held low for at least 50 ms after vdd has reached normal operation levels. as the reset pin goes high, the logic levels on sadd[4:0] are latched as the 2-wire bus address. addr[0] is the r/w bit. the circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. in receive mode, the first data byte is written to the radd virtual register, which forms the register sub-address. the radd register takes an 8-bit value that determines which of 256 possible register addresses is written to by the following byte. not all addresses are valid and many are reserved registers that must not be changed from their default values. multiple byte reads or writes will auto-increment the value in radd, but care should be taken not to access the reserved registers accidentally. following a valid chip address, the 2-wire bus stop command resets the radd register to 00. if the chip address is not recognized, the ZL10353 will ignore all activity until a valid chip address is received. the 2-wire bus start command does not reset the radd register to 00. this allows a combined 2-wire bus message, to point to a particular read register with a write command, followed immediately with a read data command. if required, this could next be followed with a write command to continue from the latest address. radd would not be sent in this case. finally, a stop command should be sent to free the bus. when the 2-wire bus is addressed (after a recognized stop command) with the read bit set, the first byte read out is the contents of register 00. 3.1.2 tuner the ZL10353 has a general purpose port that can be configured to provide a secondary 2-wire bus. see register gpp_ctl address 0x8c. master control mode is selected by setting register scan_ctl (0x62) [b3] = 1. the allocation of the pins is: gpp0 pin 35 = clk2, gpp1 pin 36 = data2. addr[7] addr[6] addr[5] addr[4] addr[3] addr[2] addr[1] not programmable sadd[4] sadd[3] sadd[2] sadd[1] sadd[0] vss vss vss vdd vdd vdd vdd
ZL10353 data sheet 13 zarlink semiconductor inc. 3.1.3 examples of 2-wire bus messages: key : s start condition w write (= 0) p stop condition r read (= 1) a acknowledge na not acknowledge italics ZL10353 output radd register address write operation - as a slave receiver: read operation - ZL10353 as a slave transmitter: write/read operation with repeated start - ZL10353 as a slave transmitter: 3.1.4 primary 2-wire bus timing figure 5 - primary 2-wire bus timing where: s = start sr = restart, i.e., start without stopping first. p = stop. sdevicew a radd a data a data a p address (n) (reg n) (reg n+1) sdevicer adata a data a data na p address (reg 0) (reg 1) (reg 2) s device w a radd a s device r adata a data na p address (n) address (reg n) (reg n+1) ps sr p low t t r t hd;sta hd;dat t t f high t t su;dat su;sta t data1 clk1 t buff t su;sto
ZL10353 data sheet 14 zarlink semiconductor inc. parameter symbol value unit min. max. clk clock frequency (primary) f clk 0 400 1 1. if operating with an external 4 mhz clock, the serial clock frequency is reduced to 100 khz maximum. khz bus free time between a stop and start condition. t buff 200 ns hold time (repeated) start condition. t hd;sta 200 ns low period of clk clock. t low 1300 ns high period of clk clock. t high 600 ns set-up time for a repeated start condition. t su;sta 200 ns data hold time (when input). t hd;dat 100 ns data set-up time t su;dat 100 ns rise time of both clk and data signals. t r note 2 2. the rise time depends on the external bus pull up resistor. loading prevents full speed operation. ns fall time of both clk and data signals, (100 pf to ground). t f 20 ns set-up time for a stop condition. t su;sto 200 ns table 3 - timing of 2-wire bus
ZL10353 data sheet 15 zarlink semiconductor inc. 3.2 mpeg 3.2.1 data output header format figure 6 - dvb transport packet header byte after decoding the 188-byte mpeg packet, it is output on the mdo pins in 188 consecutive clock cycles. additionally when the tei_en bit in the op_ctrl_0 register (0x5a) is set high (default), the tei bit of any uncorrectable packet will automatically be set to ?1?. if tei_en bit is low then tei bit will not be changed (but note that if this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high at output). tei 01000111 1st byte 2nd byte transport packet header 4 bytes 184 transport packet bytes 188 byte packet output mdo[7] mdo[0]
ZL10353 data sheet 16 zarlink semiconductor inc. 3.2.2 mpeg data output signals the mpegen bit in the config register must be set low to enable the mpeg data. the maximum movement in the packet synchronization byte position is limited to 1 output clock period. moclk will be a continuously running clock once symbol lock has been achieved, and is derived from the symbol clock. moclk is shown in figure 7 with moclkinv = ?1?, the default state, see register 0x50. all output data and signals (mdo[7:0], mostrt, moval & bkerr ) change on the negative edge of moclk (moclkinv = 1) to present stable data and signals on the positive edge of the clock. a complete packet is output on mdo[7:0] on 188 consecutive clocks and the mdo[7:0] pins will remain low during the inter-packet gaps. mostrt goes high for the first byte clock of a packet. moval goes high on the first byte of a packet and remains high until the last byte has been clocked out. bkerr goes low on the first byte of a packet where uncorrectable bytes are detected and will remain low until the last byte has been clocked out. figure 7 - mpeg output data waveforms 3.2.3 mpeg output timing maximum delay conditions: vdd = 3.0v, cvdd = 1.62v, tamb = 80 o c, output load = 10pf. minimum delay conditions: vdd = 3.6v, cvdd = 1.98v, tamb = -10 o c, output load = 10pf. moclk frequency = 45.06 mhz. mdo7:0 moclkinv=1 moclk mostrt moval bkerr tp ti 1st byte packet n 188 byte packet n 1st byte packet n+1
ZL10353 data sheet 17 zarlink semiconductor inc. 3.2.4 moclkinv = 1 figure 8 - mpeg timing - moclkinv = 1 3.2.5 moclkinv = 0 mdoswap = 0 the hold time is better when moclkinv = 1, therefore this should be used if possible. figure 9 - mpeg timing - moclkinv = 0 parameter delay conditions units maximum minimum data output delay t d 3.0 1.0 ns setup time t su 7.0 10.0 hold time t h 7.0 10.0 parameter delay conditions units maximum minimum data output delay t d 3.0 1.0 ns setup time t su 18.0 20.0 hold time t h 1.0 0.2 t d t su moclk mdo mostrt moval bkerrb } t h bkerr t d t su moclk mdo mostrt moval bkerrb } t h bkerr
ZL10353 data sheet 18 zarlink semiconductor inc. 4.0 electrical characteristics 4.1 recommended operating conditions 4.2 absolute maximum ratings note: stresses exceeding these listed under absolute maximum ratings may induce failure. exposure to absolute maximum ratings fo r extended periods may reduce reliability. functionality at or above these conditions is not implied. parameter symbol min. typ. max. units power supply voltage: periphery vdd 3.0 3.3 3.6 v core cvdd 1.62 1.8 1.98 v power supply current: periphery 1 1. current from the 3.3 v supply will be mainly dependent on the external loads. idd p 1 ma core idd c 170 ma 2 2. current given is for optimum performance, lower current is possible with reduced performance. input clock frequency 3 3. the min/max frequencies given are those supported by the oscillator cell. required system frequencies are as defined in the design manual. frequencies outside these limits are acceptable with an external clock signal. xti 16.00 20.48 25.00 mhz clk1 primary serial clock frequency 4 4. if operating with an external 4 mhz clock, the serial clock frequency is reduced to 100 khz maximum. fclk 400 khz ambient operating temperature -10 80 c maximum operating conditions parameter symbol min. max. unit power supply vdd -0.3 +3.6 v cvdd -0.3 +2.0 v voltage on input pins (5 v rated) vi -0.3 5.5 v voltage on input pins (3.3 v rated) vi -0.3 vdd + 0.3 v voltage on output pins (5 v rated) vo -0.3 5.5 v voltage on output pins (3.3 v rated) vo -0.3 vdd + 0.3 v storage temperature tstg -55 150 c operating ambient temperature top -10 80 c junction temperature tj 125 c
ZL10353 data sheet 19 zarlink semiconductor inc. 4.3 dc electrical characteristics 4.4 crystal specification and external clocking parallel resonant fundamental frequency (preferred) 20.4800 mhz tolerance over operating temperature range 150 ppm tolerance overall 200 ppm typical load capacitance 27 pf drive level 0.4 mw max equivalent series resistance <25 ? dc electrical characteristics parameter conditions pins symbol min. typ. max. unit operating voltage periphery vdd 3.0 3.3 3.6 v core cvdd 1.62 1.8 1.98 v supply current 1 1. current given is for optimum performance, lower current is possible with reduced performance. 1.62> cvdd> 1.98 iddcore 170 ma supply current sleep mode 300 a outputs output levels ioh 2ma 3.0> vdd> 3.6 mdo(7:0), moval, mostrt, moclk, status, bkerr voh 2.4 v iol 2ma 3.0> vdd> 3.6 vol 0.4 v iol 6ma 3.0> vdd> 3.6 gpp(3:0), data1, agc1, agc2, irq vol 0.4 v output capacitance not including track mdo(7:0), moval, mostrt, moclk, status, bkerr 3.0 pf gpp(3:0), data1, agc1, agc2,irq 3.6 pf output leakage (tri-state) 1 a inputs input levels 3.0> vdd> 3.6 -0.5 vin vdd+0.5v miclk, sadd(4:0) sleep, oscmode vih 2.0 v input levels 3.0> vdd> 3.6 -0.5 vin +5.5v gpp(3:0), clk1, data1, reset vih 2.0 v input levels 3.0> vdd> 3.6 capacitances do not include track all inputs vil 0.8 v input leakage current sleep, smtest, miclk, clk1, oscmode 1 a input capacitance 1.8 pf input capacitance sadd(4:0), data1, gpp(3:0) 3.6 pf
ZL10353 data sheet 20 zarlink semiconductor inc. figure 10 - crystal oscillator circuit 4.4.1 selection of external components the capacitor values used must ensure correct operation of the pierce oscillator such that the total loop gain is greater than unity. correct selection of the two capacitors is very important and the following method is recommended to obtain values for c1 and c2. 4.4.1.1 loop gain equation although oscillation may still occur if the loop gain is just above 1, a loop gain of between 5 and 25 is optimum to ensure that oscillations will occur across all variations in temperature, process and supply voltage, and that the circuit will exhibit good start-up characteristics. equation 1 - equation 2 - 4.4.1.2 list of equation parameters a total loop gain (between 5 and 25) cin c1 + cpar cout c2 + cpar cpar parasitic capacitance associated with each oscillator pin (xti and xto). it consists of track capacitances, package capacitance and cell input capacitance. normally cpar 4pf. zo 9.143 k ? - output impedance of amplifier at 1.8 v operation - typical gm 8.736 ma/v - transconductance of amplifier at 1.8 v operation -typical rf 2.3 m ? - internal feedback resistor esr maximum equivalent series resistance of crystal - given by crystal manufacturer ( ? ) f fundamental frequency of crystal (hz) xti xt0 xti c2 oscmode c1 - a = c out .g m c in c out + c in r f .c in + 1 z in -1 1 z o + - z in = 1 (2. .f.c out ) 2 .esr
ZL10353 data sheet 21 zarlink semiconductor inc. 4.4.1.3 calculating crystal power dissipation to calculate the power dissipated in a crystal the following equation can be used. equation 3 - pc = power dissipated in crystal at resonant frequency (w) vpp = maximum peak to peak output swing of amplifier is 1.8 v for all cvdd zin = crystal network impedance (see equation 2) 4.4.1.4 capacitor values using the loop gain limits (5 < a < 25), the maximum and minimum values for c1 and c2 can be calculated with equation 4 below. equation 4 - note: equation 4 was derived from equation 1 and equation 2 using the premise that c1 = c2. within these limits, any value for c1 and c2 can now be selected. normally c1 and c2 are chosen such that the resulting crystal load capacitance c l (see equation 5) is close to the crystal manufacturers recommended c l (standard values for c l are 15 pf, 20 pf and 30 pf). the crystal will then operate very near its specified frequency. equation 5 - c par12 = parasitic capacitance between the xti and xto pins. it consists of the ic package?s pin-to-pin capacitance (including any socket used) and the printed circuit board?s track-to-track capacitance. c par12 2pf. if some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer?s recommended c l may be acceptable. larger values of c l tend to reduce the influence of circuit variations and tolerances on frequency stability. smaller values of c l tend to reduce startup time and crystal power dissipation. care must however be taken that c l does not fall outside the crystal pulling range or the circuit may fail to start up altogether. it is also possible to quote c l to the crystal manufacturer who can then cut a crystal to order which will resonate, under the specified load conditions, at the desired frequency. finally the power dissipation in the crystal must be checked. if pc is too high c1 and c2 must be reduced. if this is not feasible c2 alone may be reduced. unbalancing c1 and c2 will, however, require checking if the loop gain condition is still satisfied. this must be done using equation 1. p c = 8.z in v pp 2 c in = c out = g m a 2 r f 1 z o 1 (2. .f) 2 .esr when: c 1 = c 2 = c out - c par -- . - c l = c out . c in c out + c in + c par12 note: 2 > c 2 c 1 > 0.5
ZL10353 data sheet 22 zarlink semiconductor inc. 4.4.1.5 oscillator/clock application notes ? on the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible. other signal tracks must not be allowed to cross through this area. the component tracks should preferably be ringed by a ground track connected to the chip ground (0 v) on adjacent pins either side of the crystal pins. it is also advisable to provide a ground plane for the circuit to reduce noise. ? external clock signals, applied to xti and/or xto, must not exceed the cell supply limits (i.e., 0v and cvdd) and current into or out of xti and/or xto must be limited to less than 10ma to avoid damaging the cell?s amplitude clamping circuit. ? an external, dc coupled, single ended square wave clock signal may be applied to xti if oscmode = 0. to limit the current taken from the signal source a resistor should be placed between the clock source and xti . the recommended value for this series resistor is 470 ? for a clock signal switching between 0 v and cvdd. the current the clock source needs to source/sink is then < 1.9 ma. the xto pin must be left unconnected in this configuration. ? ac coupling of a single ended external clock to xti , with oscmode = 0, is not recommended. the duty cycle of the oscout signal cannot be guaranteed in such a configuration. ? ac coupling of a single ended external clock to xti , with oscmode = 1, is possible. it is recommended that the circuit shown in figure 11 be used to correctly bias the oscillator inputs: the common-mode voltage vcm for xti and xto, (set by the 36 k ? and 22 k ? resistors) must be 800 mv < vcm < cvdd and the amplitude vpp of the clock signal must be >100 mv. figure 11 - external clocking via ac coupling ? external, differential clock signals may be applied to xti and xto if oscmode = 1. the common-mode voltage vcm for the differential clock signals must be 800 mv < vcm < cvdd, and the peak-to-peak signal amplitude vpp must be >100 mv. it is recommended that differential clock signals have vcm = 1.0v. for vpp > 400 mv a resistor of > 390 ? in series with xti or xto may be required to limit the current taken from or supplied to the clock sources. external clock 10nf xti 100k 10nf 22k 36k xto vdd oscmode
ZL10353 design manual 23 zarlink semiconductor inc. 5.0 application circuit figure 12 - typical application circuit

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